1. Field of the Invention
The present invention relates to an equalizer circuit.
2. Description of the Related Art
When a single-ended signal or a differential signal is transmitted from a transmission device (transmitter) to a reception device (receiver) via a transmission line, waveform distortion occurs due to loss (transmission loss) that occurs in the transmission line. The transmission loss markedly increases as the length (transmission length) of the transmission line becomes longer. In general, such a long transmission line has approximately the effect of low-pass filter on the signal. Accordingly, when a rectangular wave signal is transmitted from a transmitter, a distorted waveform is observed at the reception terminal of the receiver.
In order to solve such a problem, in some cases, an equalizer circuit is provided so as to correct the transmitted waveform by canceling out the waveform distortion that occurs due to transmission loss (which will also be referred to as “pre-emphasis” or “pre-distortion”). As an example of pre-emphasis, processing is performed in which the high frequency component of the original signal to be transmitted is extracted so as to generate an emphasis component, and the emphasis component thus extracted is superimposed on the original signal, or the like.
In a case in which one cycle of the transmission signal (which will also be referred to as a “unit interval UI” hereafter) is shorter than the time constant of the waveform distortion, a discrete-time equalizer is effectively employed, which is configured to add the emphasis components in increments of UIs. In a case in which a binary transmission signal is equalized, and in a case in which a bit stream is transmitted with a constant UI, such an equalizer can be implemented in the form of a simple circuit.
[Patent Document 1]
International Publication WO 05/121827 pamphlet
An automatic test apparatus (Automatic Test Equipment) configured to test a semiconductor device includes a unit which is a so-called timing controller. Such a timing controller provides a function of changing, as desired, the timing of each edge of a signal to be applied to a device under test (DUT), i.e., the UI, in increments of bits in a real time manner. This function is referred to as “RTTC (Real Time Timing Control)” or “on the fly operation”. As a function similar to RTTC, in some cases, the ATE has a jitter injection function as disclosed in Patent Document 1, for example. The jitter injection function is a function in which, in order to evaluate the jitter tolerance of the DUT, a signal containing a known jitter is supplied from the ATE to the DUT, and the ATE judges whether or not the DUT can receive the signal correctly. Based upon thinking similar to RTTC, the jitter injection can be performed by dynamically changing a delay applied to each edge of a signal.
With such an ATE having an RTTC function, the UI is dynamically changed in a real time manner. Accordingly, conventional discrete-time equalizers, which are designed under the assumption that the UI is maintained at a constant value, cannot be employed.